\doxysubsubsection{TIM Exported Constants }
\hypertarget{group___t_i_m___exported___constants}{}\label{group___t_i_m___exported___constants}\index{TIM Exported Constants@{TIM Exported Constants}}
\doxysubsubsubsubsection*{Topics}
\begin{DoxyCompactItemize}
\item 
\mbox{\hyperlink{group___t_i_m___clear_input___source}{TIM Clear Input Source}}
\item 
\mbox{\hyperlink{group___t_i_m___d_m_a___base__address}{TIM DMA Base Address}}
\item 
\mbox{\hyperlink{group___t_i_m___event___source}{TIM Event Source}}
\item 
\mbox{\hyperlink{group___t_i_m___input___channel___polarity}{TIM Input Channel polarity}}
\item 
\mbox{\hyperlink{group___t_i_m___e_t_r___polarity}{TIM ETR Polarity}}
\item 
\mbox{\hyperlink{group___t_i_m___e_t_r___prescaler}{TIM ETR Prescaler}}
\item 
\mbox{\hyperlink{group___t_i_m___counter___mode}{TIM Counter Mode}}
\item 
\mbox{\hyperlink{group___t_i_m___update___interrupt___flag___remap}{TIM Update Interrupt Flag Remap}}
\item 
\mbox{\hyperlink{group___t_i_m___clock_division}{TIM Clock Division}}
\item 
\mbox{\hyperlink{group___t_i_m___output___compare___state}{TIM Output Compare State}}
\item 
\mbox{\hyperlink{group___t_i_m___auto_reload_preload}{TIM Auto-\/\+Reload Preload}}
\item 
\mbox{\hyperlink{group___t_i_m___output___fast___state}{TIM Output Fast State}}
\item 
\mbox{\hyperlink{group___t_i_m___output___compare___n___state}{TIM Complementary Output Compare State}}
\item 
\mbox{\hyperlink{group___t_i_m___output___compare___polarity}{TIM Output Compare Polarity}}
\item 
\mbox{\hyperlink{group___t_i_m___output___compare___n___polarity}{TIM Complementary Output Compare Polarity}}
\item 
\mbox{\hyperlink{group___t_i_m___output___compare___idle___state}{TIM Output Compare Idle State}}
\item 
\mbox{\hyperlink{group___t_i_m___output___compare___n___idle___state}{TIM Complementary Output Compare Idle State}}
\item 
\mbox{\hyperlink{group___t_i_m___input___capture___polarity}{TIM Input Capture Polarity}}
\item 
\mbox{\hyperlink{group___t_i_m___encoder___input___polarity}{TIM Encoder Input Polarity}}
\item 
\mbox{\hyperlink{group___t_i_m___input___capture___selection}{TIM Input Capture Selection}}
\item 
\mbox{\hyperlink{group___t_i_m___input___capture___prescaler}{TIM Input Capture Prescaler}}
\item 
\mbox{\hyperlink{group___t_i_m___one___pulse___mode}{TIM One Pulse Mode}}
\item 
\mbox{\hyperlink{group___t_i_m___encoder___mode}{TIM Encoder Mode}}
\item 
\mbox{\hyperlink{group___t_i_m___interrupt__definition}{TIM interrupt Definition}}
\item 
\mbox{\hyperlink{group___t_i_m___commutation___source}{TIM Commutation Source}}
\item 
\mbox{\hyperlink{group___t_i_m___d_m_a__sources}{TIM DMA Sources}}
\item 
\mbox{\hyperlink{group___t_i_m___c_c___d_m_a___request}{CCx DMA request selection}}
\item 
\mbox{\hyperlink{group___t_i_m___flag__definition}{TIM Flag Definition}}
\item 
\mbox{\hyperlink{group___t_i_m___channel}{TIM Channel}}
\item 
\mbox{\hyperlink{group___t_i_m___clock___source}{TIM Clock Source}}
\item 
\mbox{\hyperlink{group___t_i_m___clock___polarity}{TIM Clock Polarity}}
\item 
\mbox{\hyperlink{group___t_i_m___clock___prescaler}{TIM Clock Prescaler}}
\item 
\mbox{\hyperlink{group___t_i_m___clear_input___polarity}{TIM Clear Input Polarity}}
\item 
\mbox{\hyperlink{group___t_i_m___clear_input___prescaler}{TIM Clear Input Prescaler}}
\item 
\mbox{\hyperlink{group___t_i_m___o_s_s_r___off___state___selection__for___run__mode__state}{TIM OSSR Off\+State Selection for Run mode state}}
\item 
\mbox{\hyperlink{group___t_i_m___o_s_s_i___off___state___selection__for___idle__mode__state}{TIM OSSI Off\+State Selection for Idle mode state}}
\item 
\mbox{\hyperlink{group___t_i_m___lock__level}{TIM Lock level}}
\item 
\mbox{\hyperlink{group___t_i_m___break___input__enable__disable}{TIM Break Input Enable}}
\item 
\mbox{\hyperlink{group___t_i_m___break___polarity}{TIM Break Input Polarity}}
\item 
\mbox{\hyperlink{group___t_i_m___break2___input__enable__disable}{TIM Break input 2 Enable}}
\item 
\mbox{\hyperlink{group___t_i_m___break2___polarity}{TIM Break Input 2 Polarity}}
\item 
\mbox{\hyperlink{group___t_i_m___a_o_e___bit___set___reset}{TIM Automatic Output Enable}}
\item 
\mbox{\hyperlink{group___t_i_m___group___channel5}{TIM Group Channel 5 and Channel 1, 2 or 3}}
\item 
\mbox{\hyperlink{group___t_i_m___master___mode___selection}{TIM Master Mode Selection}}
\item 
\mbox{\hyperlink{group___t_i_m___master___mode___selection__2}{TIM Master Mode Selection 2 (\+TRGO2)}}
\item 
\mbox{\hyperlink{group___t_i_m___master___slave___mode}{TIM Master/\+Slave Mode}}
\item 
\mbox{\hyperlink{group___t_i_m___slave___mode}{TIM Slave mode}}
\item 
\mbox{\hyperlink{group___t_i_m___output___compare__and___p_w_m__modes}{TIM Output Compare and PWM Modes}}
\item 
\mbox{\hyperlink{group___t_i_m___trigger___selection}{TIM Trigger Selection}}
\item 
\mbox{\hyperlink{group___t_i_m___trigger___polarity}{TIM Trigger Polarity}}
\item 
\mbox{\hyperlink{group___t_i_m___trigger___prescaler}{TIM Trigger Prescaler}}
\item 
\mbox{\hyperlink{group___t_i_m___t_i1___selection}{TIM TI1 Input Selection}}
\item 
\mbox{\hyperlink{group___t_i_m___d_m_a___burst___length}{TIM DMA Burst Length}}
\item 
\mbox{\hyperlink{group___d_m_a___handle__index}{TIM DMA Handle Index}}
\item 
\mbox{\hyperlink{group___channel___c_c___state}{TIM Capture/\+Compare Channel State}}
\item 
\mbox{\hyperlink{group___t_i_m___break___system}{TIM Break System}}
\end{DoxyCompactItemize}


\doxysubsubsubsection{Detailed Description}
\input{group___t_i_m___clear_input___source}
\input{group___t_i_m___d_m_a___base__address}
\input{group___t_i_m___event___source}
\input{group___t_i_m___input___channel___polarity}
\input{group___t_i_m___e_t_r___polarity}
\input{group___t_i_m___e_t_r___prescaler}
\input{group___t_i_m___counter___mode}
\input{group___t_i_m___update___interrupt___flag___remap}
\input{group___t_i_m___clock_division}
\input{group___t_i_m___output___compare___state}
\input{group___t_i_m___auto_reload_preload}
\input{group___t_i_m___output___fast___state}
\input{group___t_i_m___output___compare___n___state}
\input{group___t_i_m___output___compare___polarity}
\input{group___t_i_m___output___compare___n___polarity}
\input{group___t_i_m___output___compare___idle___state}
\input{group___t_i_m___output___compare___n___idle___state}
\input{group___t_i_m___input___capture___polarity}
\input{group___t_i_m___encoder___input___polarity}
\input{group___t_i_m___input___capture___selection}
\input{group___t_i_m___input___capture___prescaler}
\input{group___t_i_m___one___pulse___mode}
\input{group___t_i_m___encoder___mode}
\input{group___t_i_m___interrupt__definition}
\input{group___t_i_m___commutation___source}
\input{group___t_i_m___d_m_a__sources}
\input{group___t_i_m___c_c___d_m_a___request}
\input{group___t_i_m___flag__definition}
\input{group___t_i_m___channel}
\input{group___t_i_m___clock___source}
\input{group___t_i_m___clock___polarity}
\input{group___t_i_m___clock___prescaler}
\input{group___t_i_m___clear_input___polarity}
\input{group___t_i_m___clear_input___prescaler}
\input{group___t_i_m___o_s_s_r___off___state___selection__for___run__mode__state}
\input{group___t_i_m___o_s_s_i___off___state___selection__for___idle__mode__state}
\input{group___t_i_m___lock__level}
\input{group___t_i_m___break___input__enable__disable}
\input{group___t_i_m___break___polarity}
\input{group___t_i_m___break2___input__enable__disable}
\input{group___t_i_m___break2___polarity}
\input{group___t_i_m___a_o_e___bit___set___reset}
\input{group___t_i_m___group___channel5}
\input{group___t_i_m___master___mode___selection}
\input{group___t_i_m___master___mode___selection__2}
\input{group___t_i_m___master___slave___mode}
\input{group___t_i_m___slave___mode}
\input{group___t_i_m___output___compare__and___p_w_m__modes}
\input{group___t_i_m___trigger___selection}
\input{group___t_i_m___trigger___polarity}
\input{group___t_i_m___trigger___prescaler}
\input{group___t_i_m___t_i1___selection}
\input{group___t_i_m___d_m_a___burst___length}
\input{group___d_m_a___handle__index}
\input{group___channel___c_c___state}
\input{group___t_i_m___break___system}
